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The effect of contact resistance cannot be neglected as the device is scaled down. Mapping is used to facilitate the extraction of parallelism along with efficient data reuse. VLSI circuits can be both combinational and sequential. School of Ayurveda Amritapuri. The technique of clock gating is used to reduce the clock power consumption by cutting off the idle clock cycles. The unfolding transformation is incorporated along with retimed DG to improve the parallel processing of the system. The high carrier mobility of these materials on a substrate at room temperature and high electron velocity and thermal conductivity, are the motivation to explore the possibility to use FETs based on these materials. This paper presents a method of identifying the optimal solution directly and through a logical procedure.

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